System, method and memory device providing data scrambling compatible with on-chip copy operation

ABSTRACT

Data scrambling techniques implemented externally to a flash memory device are disclosed which can be used in concert with flash memory on-chip copy functionality operating internally to the flash device, thus supporting high performance copying operations. All the data stored in the flash may be scrambled, including headers and control structures. Robust file system operation may be achieved, including the capability to tolerate a power loss at any time, and yet be able to relocate data internally within the flash without having to de-scramble and then re-scramble the data. An exemplary hardware based solution has little or no impact on overall system performance, and may be implemented at very low incremental cost to increase overall system reliability. The data scrambling technique preferably uses a logical address, such as logical block address or logical page address, rather than a physical address, to determine a seed scrambling key.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 U.S.C. §119(e) of U.S.Provisional Application No. 61/018,096 filed on Dec. 31, 2007 andentitled “System, Apparatus, and Method for Memory Device DataScrambling Usable with On-Chip Copy Operation” by Jason T. Lin, StevenS. Cheng, and Shai Traister, which application is incorporated herein byreference in its entirety.

BACKGROUND

The present invention relates generally to flash memory storage systems,and more specifically to such a system in which data to be written tothe flash memory is scrambled to help reduce certain datapattern-dependent sensitivities and disturbance effects.

A “flash file system” provides a system of data storage and manipulationon a flash memory device that allows the device to emulate a magneticdisk. A flash file system enables applications or operating systems tointeract with a flash memory device not using physical addresses butrather using logical addresses (sometimes called virtual addresses). Anintermediate software layer between the software application and thephysical memory system provides a mapping between logical addresses andphysical addresses. Some systems that implement logical-to-physicaladdress mapping are described in U.S. Pat. No. 5,404,485 to Ban, in U.S.Pat. No. 5,937,425 to Ban, and in U.S. Pat. No. 6,591,330 to Lasser, allthree of which patents are incorporated herein by reference in theirentirety.

NAND flash memories are inherently susceptible to specific datapatterns. For example, programming many cells on the same bit line tothe same data state, or many cells on the same word line to the samedata state, may cause program disturb effects which may alter the cellcharge distribution and shift one or more cells to a different datastate. Such fixed repetitive data patterns are not uncommon in bitpatterns frequently written to flash memories, particularly thosewritten to certain blocks, such as control blocks, within a flash filesystem. Such control blocks are used by the file system, for example, tokeep track of logical-to-physical address mapping information, and otherinformation about the various data blocks. At times, programming even afew word lines to specific data states may also cause such disturbeffects. These disturb effects, as well as others, are particularlyproblematic in memory arrays storing multiple bits per cell (i.e., MBCarrays), also known as “multiple level cell” (MLC) arrays, and theseeffects can cause one or more cells to generate a read error as afunction of specific user data patterns. Certain program disturb effectsare described in U.S. Pat. No. 7,023,739 to Chen, et al., (the '739patent), the disclosure of which is incorporated herein by reference inits entirety.

To address this issue, techniques have been devised using system leveldata scrambling or randomization to eliminate the particularlyproblematic data patterns in the user data and control blocks beforeprogramming into a flash device. In this context, the act of scramblingor randomizing data refers to breaking up the bit patterns associatedwith the memory cell states along memory bit-lines and word-lines.However, such data scrambling techniques implemented outside the NANDmemory are incompatible with the use of Flash Memory On-Chip-Copy orCopy-Back operations, and cannot achieve the system performance thatwould otherwise be attainable. Such an on-chip-copy operates on chunksof data to autonomously relocate data from one physical memory locationto another physical memory location. This provides higher performanceand requires less power consumption than is achievable without usingon-chip copy operation, in which data is read from the device andcommunicated off-chip to a companion device (e.g., a flash controllerdevice), then re-written into a different physical location of the NANDmemory. However, an on-chip copy operation performed on data that isscrambled based on a physical memory address will unintentionallyassociate the scrambled data with a new key/seed, and results in theinability to properly descramble the data using the incorrect newkey/seed to retrieve the original intended data.

SUMMARY

The present invention provides for data scrambling techniquesimplemented externally to a flash memory device which can be used inconcert with flash memory on-chip copy functionality operatinginternally to the flash device, thus supporting high performance copyingoperations. Many modern flash memory sub-systems implement “flash filesystems” which frequently utilize garbage collection techniques, and canbenefit greatly from such on-chip copy functionality. In addition, thetechniques may be implemented to provide, for example, a hardware basedsolution which has little or no impact on overall system performance,and which may be implemented at very low incremental cost, to provide acost-effective solution for increasing overall system reliability.

The data scrambling technique preferably uses a logical address, such asa logical page address, rather than a physical page address, todetermine a seed scrambling key. The logical page address is determinedfrom the logical block address of the data, and thus does not restrictthe physical placement of the scrambled data in memory. As a result,on-chip copy operations may be used. Since the logical page address ofthe data remains unchanged even if the data is relocated by an on-chipcopy operation, the same seed scrambling key may be used to descramblethe data. This seed scrambling key is used to scramble the user data ina particular portion of the block, but as additional data is writtenacross a single word line, and as additional data is written along bitlines, the scrambling key is deterministically varied to generally“randomize” the data states.

The invention also provides for robust file system operation, includingthe capability to tolerate a power loss at any time, and be able tore-initialize a flash memory and reconstruct the mapping of the variousblocks stored therewithin, to properly descramble and read back data inorder to identify data types and data relocations due to on-chip-copyoperations. All the data stored in the flash may be scrambled, includingheaders and control structures. The scrambling key information may bestored in the page headers to enable extraction of the scrambling keyitself, from the scrambled data, during initialization. In someembodiments, different scrambling methods are used to scrambleinformation in control structures to support initialization and debugprocesses.

In certain embodiments, the data scrambling can be done effectively byhardware, firmware, or software using a simplistic method involving XORlogic and a deterministic number of Scrambling Keys by bitwise rotatinga predetermined initial Scrambling Key Seed, thereby creating a sequenceof revolving scrambling keys, each with an assigned key number. Thescrambling keys (i.e., “scrambler” keys) can be deduced for any logicalgroup of data with knowledge of the first scrambling key number used inthe logical group, which may be referred to as the Starting Key Number(SKN).

SKN's can be associated with the logical group memory address and usedfor scrambling data. The SKN itself, as well as other header (oroverhead) information, can be scrambled in the same method as user databits. In some embodiments, the Flash Controller Firmware (FW) or SystemHost Software need only set the SKN at the beginning of each memorytransaction. Within the transaction, the scrambler may be configured toautomatically generate subsequent Scrambling Keys as additional groupsof data are written or read.

ECC encoding can be applied to the scrambled SKN bits separately orapplied together with the associated scrambled user data bits. ECCencoded scrambled SKN bits and ECC encoded scrambled user data bits maybe then stored in the Flash Memory. ECC generation/correction can bedone either before or after scrambling/descrambling. The ECC paritybytes may or may not be scrambled, even though the header and dataportions are scrambled.

In some embodiments, the Flash Controller Firmware or System HostSoftware having prior knowledge of Scrambler Key generation mechanismand data scrambling method can: (a) mimic the Data Scrambler operations;(b) efficiently build a table (e.g., 32 entries) forward mapping desiredscrambled SKN's to logical addresses (e.g., using the default seed); and(c) efficiently build a table with reverse mapping of logical addressesto desired scrambled SKN's.

During system initialization, an exemplary system may perform thefollowing to identify the data types and logical grouping locationsstored in Flash Memory: (a) Flash Controller Firmware (FW) or SystemHost Software generates the forward and reverse mapping tables for thedesired scrambled SKN's; (b) with the Hardware Scrambler disabled, thefirst sector of each memory block is scanned to extract the firstscrambled SKN stored in that memory block (e.g., within the firstseveral bytes of each sector); (c) using the extracted scrambled SKN,the Flash Controller Firmware or System Host Software looks up thereverse mapping table to determine the unscrambled SKN; (d) with theHardware Scrambler enabled, the first sector is read again butdescrambled using the unscrambled SKN as the key (alternatively, the FWmay use the SKN and perform the descrambling of the header withoutreading the data again); and (e) the memory block type is identified andstored in the Flash Controller RAM.

After system initialization, the Flash Controller Firmware or SystemHost Software may control the assignment of physical memory locationsfor storing logical groups of data, use the logical group address as thescrambling and descrambling key/seed, and use the forward mapping tableof desired scrambled SKN's to store the scrambled SKN associated withthe logical group in the Flash Memory. The Flash Controller Firmware orSystem Host Software may perform memory read operations using thelogical group addresses as the key/seed for descrambling the user databits. Logical sector data may be physically relocated on the FlashMemory by on-chip-copy operation(s) at any time. The controller is awarewhen an on-chip copy is performed, and can re-map the data accordingly.

In one aspect the invention provides a method for storing information ina non-volatile memory which, in an exemplary embodiment, includesdetermining a starting key based upon a seed key and a logical pageaddress associated with a group of data; randomizing the group of datausing a deterministic sequence of keys corresponding to the startingkey; and storing the randomized group of data into a physical page ofthe non-volatile memory.

In another aspect the invention provides a method for storinginformation in a non-volatile memory which, in an exemplary embodiment,includes determining a page offset number using a logical block addressof a memory page; determining a starting key based upon a seed key andthe page offset number; scrambling page data using a deterministicsequence of scrambling keys corresponding to the starting key; storinginto a header of a physical page of the non-volatile memory anidentifier corresponding to the page offset number; and storing thescrambled page data into the physical page.

In another aspect the invention provides an apparatus which, in anexemplary embodiment, includes a non-volatile memory, and a memorycontroller configured to determine a starting key based upon a seed keyand a logical page address associated with a group of data; randomizethe group of data using a deterministic sequence of keys correspondingto the starting key; and store the randomized group of data into aphysical page of the non-volatile memory.

The methods of the present invention may be implemented by software, byhardware, or by a combination of both. Such software may be softwareexecuted on a host computer which reads and writes the data (e.g.,within a software device driver supporting the storage device), or maybe firmware executed within a memory controller that interacts with thehost computer and controls the memory media. Such hardware may beimplemented either within the memory controller or within the memorymedia, irrespective of whether the memory controller and the memorymedia reside on two separate dies or reside on a common die. All of theabove configurations and variations are within the scope of thisinvention.

The foregoing summary is intended to help introduce the invention, andshould not be viewed as limiting, as the invention is defined by theclaims. Moreover, the inventive concepts and embodiments describedherein are specifically contemplated to be used alone as well as invarious combinations. Accordingly, other embodiments, variations, andimprovements not described herein are not necessarily excluded from thescope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerousobjects, features, and advantages made apparent to those skilled in theart by referencing the accompanying drawings.

FIG. 1, labeled prior art, is a schematic diagram of a NAND memoryarray.

FIGS. 2A, 2B, and 2C are diagrams depicting various programmed memorystates in a single-bit-per-cell memory, and in a multiple-bit-per-cellmemory.

FIGS. 3A and 3B depict conceptually a scrambler block and a descramblerblock in accordance with the present invention.

FIG. 4 is a diagram of an exemplary sequence of 8-bit scrambling keys.

FIG. 5 is a table depicting an exemplary sequence of 32-bit scramblingkeys.

FIG. 6 is a diagram depicting the use of different scrambling keys fordifferent words of a page, and for different pages.

FIG. 7 is a diagram illustrating a sector boundary falling in the middleof a scrambling key.

FIG. 8 is a table illustrating exemplary values of several scramblingparameters relevant to each of 16 sectors within a physical page.

FIG. 9 is a diagram of another exemplary sequence of 8-bit scramblingkeys.

FIG. 10 is another diagram illustrating a sector boundary falling in themiddle of a scrambling key.

FIG. 11 is a table illustrating exemplary values of several scramblingparameters relevant to each of 4 ECC pages within a physical page.

FIG. 12 is a table illustrating exemplary SKN values for each of 4 ECCpages within a physical page, and for each of 32 physical pages.

FIG. 13 is a diagram depicting an exemplary header format for asingle-sector ECC page.

FIG. 14 is a diagram depicting another exemplary header format for a 2KByte ECC page.

FIG. 15 is an exemplary page mapping table in accordance with someembodiments of the present invention.

FIG. 16 is an exemplary SKN table in accordance with some embodiments ofthe present invention.

FIG. 17 is a flowchart of exemplary operation of a scrambler inaccordance with some embodiments of the present invention.

FIG. 18 is a diagram of an exemplary scrambler block in accordance withsome embodiments of the present invention.

FIG. 19 is a table depicting memory cell states of unscrambled repeating0×FF data patterns.

FIG. 20 is a table depicting memory cell states of scrambled datacorresponding to that shown in FIG. 19, after scrambling in accordancewith certain embodiments of the present invention.

The use of the same reference symbols in different drawings indicatessimilar or identical items.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Referring now to FIG. 1, a schematic diagram is shown representing aportion of a typical NAND memory array 100. The portion shown mayrepresent a two-dimensional array having only one plane of memory cells,or may represent one level of three-dimensional memory array having morethan one plane of memory cells stacked on top of each other. Theexemplary NAND string 102 includes thirty-two memory cell transistorsconnected in series, each gated by a respective one of a plurality ofthirty-two word lines 111 (individually labeled WL0, WL1, . . . , WL30,WL31). The NAND string 102 also includes a block select device 114 forcoupling one end of the NAND string to a bit line 103 in accordance witha block select signal BS0 conveyed on node 113, and further includes asecond block select device 116 for coupling the other end of the NANDstring to a shared bias node 101 in accordance with a block selectsignal BS1 conveyed on node 115.

Each NAND string 102, 104, 106 is disposed within the same block 124within the memory array, and each is respectively coupled to itsassociated bit line 103, 105, 107. The memory cells in the NAND strings(i.e., those gated by one of the word lines) typically incorporate afloating gate structure, or may incorporate a charge storage dielectriclayer between the gate and the underlying channel, so that the thresholdvoltage of the memory cell device may be altered by programming anderasure. The various block select devices (e.g., 114, 116) are typicallynormal MOS devices (i.e., non-programmable), but in certain memorytechnologies may be fabricated identically to the memory cell devices.While this exemplary NAND array 100 shows thirty-two word lines in aNAND block, other numbers of word lines per block are possible, such as16, 64, 88, or any other value, although a number equal to an integralpower of two is typically implemented.

Thus, a typical NAND memory cell array may be generalized as having amemory cell represented by the intersection of each bit-line andword-line. Traditionally, each memory cell stores one bit ofinformation, which is accomplished by supporting two states of thememory cell. One state represents a logical “0” and the other staterepresents a logical “1”. Frequently, the two states may be implementedby having a floating gate situated above the cell's channel (the areaconnecting the source and drain elements of the cell's transistor), andhaving two valid states for the amount of charge stored within thefloating gate. Typically, one state is with zero charge in the floatinggate and is the initial unwritten state of the cell after being erased(commonly defined to represent the “1” state) and another state is withsome amount of negative charge in the floating gate (commonly defined torepresent the “0” state). Having negative charge in the gate causes thethreshold voltage of the cell's transistor (i.e. the voltage that has tobe applied to the transistor's control gate in order to cause thetransistor to conduct) to increase. It is then possible to read thestored bit by checking the threshold voltage of the cell—if thethreshold voltage is in the higher state then the bit value is “0” andif the threshold voltage is in the lower state then the bit value is“1”. Actually there is no need to accurately read the cell's thresholdvoltage—all that is needed is to correctly identify in which of the twostates the cell is currently located. For that purpose it is enough tomake a comparison against a reference voltage value that is in themiddle between the two states, and thus to determine if the cell'sthreshold voltage is below or above this reference value.

FIG. 2A shows graphically how this works. Specifically, FIG. 2A showsthe distribution of the threshold voltages of a large population ofcells. Because the cells in a flash device are not exactly identical intheir characteristics and behavior (due, for example, to smallvariations in impurities concentrations or to defects in the siliconstructure), applying the same programming operation to all the cellsdoes not cause all of the cells to have exactly the same thresholdvoltage. (Note that, for historical reasons, writing data to a flashmemory is commonly referred to as “programming” the flash memory.)Instead, the threshold voltage is distributed. Cells storing a value of“1” typically have a negative threshold voltage, such that most of thecells have a threshold voltage close to the value shown by the left peak120, with some smaller numbers of cells having lower or higher thresholdvoltages. Similarly, cells storing a value of “0” typically have apositive threshold voltage, such that most of the cells have a thresholdvoltage close to the value shown by the right peak 122, with somesmaller numbers of cells having lower or higher threshold voltages.

It is increasingly common for memory cells to store more than 1 bit ofinformation, using a technique conventionally called “Multi Level Cells”or MLC for short. However, this nomenclature is misleading, because theprevious type of flash cells also has more than one level: they have twolevels, as described above. Therefore, the two kinds of flash cells arereferred to herein as “Single Bit Cells” (SBC) and “Multi-Bit Cells”(MBC). The improvement brought by the MBC flash is the storing of two(or more) bits in each cell. In order to simplify the explanations, thetwo-bit case is emphasized herein. It should however be understood thepresent invention is equally applicable to flash memory devices thatsupport any number of bits per cell. In order for a single memory cellto store two bits of information, the memory cell must be able to beprogrammed in one of four different states. As the cell's “state” isrepresented by its threshold voltage, it is clear an MBC cell shouldsupport four different valid ranges for its threshold voltage. FIG. 2Bshows an exemplary threshold voltage distribution for a typical MBCcell. As expected, FIG. 2B has four peaks 130, 132, 134, 136, eachcorresponding to one state. As for the SBC case, each state is actuallya range and not a single number. When reading the cell's contents, allthat must be guaranteed is that the range that the cell's thresholdvoltage falls within is correctly identified. An example of an MBC flashdevice is described in U.S. Pat. No. 5,434,825 to Harari, the disclosureof which is incorporated herein by reference in its entirety.

When encoding two bits in an MBC cell by the four states, it is commonto have the left-most state, peak 130, (typically having a negativethreshold voltage) represent the case of both bits having a value of“1”. In the discussion below, the following notation is used—the twobits of a cell are called the “lower bit” and the “upper bit”. Anexplicit value of the bits is written in the form [“upper bit” “lowerbit”], with the lower bit value on the right. So the case of the lowerbit being “0” and the upper bit being “1” is written as “10”. It shouldbe understood that the selection of this terminology and notation isarbitrary, and other names and encodings are possible. Using thisnotation, the left-most state represents the case of “11”. The otherthree states are typically assigned by the following order from left toright—“10”, “00”, “01”. An example of MBC NAND flash device using suchencoding is described in U.S. Pat. No. 6,522,580 to Chen, the disclosureof which is incorporated herein by reference in its entirety. See inparticular FIG. 8 of the Chen patent. The four such states may bereferred to simply as E, A, B, and C. It should be noted though thatthere is nothing limiting about this assignment of the states, and thatany other ordering can be used. When reading an MBC cell's content, therange that the cell's threshold voltage falls within must be identifiedcorrectly; but in this case this cannot be achieved by comparing to onereference voltage, and several comparisons may be necessary.

Another state assignment is depicted in FIG. 2C, which may be referredto as LM Mode. In this mode, there are four peaks 140, 142, 144, 146 (inorder from left to right) corresponding respectively to memory states“11”, “01”, “00”, “10”. These four states may again be referred tosimply as E, A, B, and C. The lower page is typically programmed first,and if a “0” is to be programmed, results in an intermediate LM state,labeled as peak 148. When the upper page is to be programmed, if theupper bit is a “0”, either the E state 140 is programmed to the A state142, or the LM state 148 is programmed to the B state 144. If the upperbit is a “1”, then the LM state 148 is programmed to the C state 146.

This LM Mode provides several advantages over the Conventional mode.First, there may be less programming stress since the programming timein the LM mode may be less than in the conventional mode (e.g.,programming a memory cell in the conventional mode from the E state 130to the C state 136 requires a long time to shift the threshold voltageof the memory cell, and stresses neighboring cells the entire time,whereas each of the threshold shifts in the LM mode are smaller inmagnitude), and therefore less program disturb, and greater reliability.In addition, if using only the lower page, the separation between the Estate 140 and the intermediate LM state 148 is larger than theseparation between the E state 130 and A state 132 in the conventionalmode, thereby resulting in greater signal margins in the memory cell.Lastly, the width of peak 148 can be wider than the width of peak 132 inthe conventional mode, which allows lower page programming to occur morequickly since the resulting final threshold value need not be controlledas exactingly as in the conventional mode.

MBC devices provide a great advantage of cost—using a similarly sizedcell an MBC device stores two bits rather than one. However, there mayalso some drawbacks to using MBC flash—the average read and write timesof MBC memories are longer than of SBC memories, resulting in lowerperformance. Also, the reliability of MBC is lower than SBC. This caneasily be understood—the differences between the threshold voltageranges in MBC are much smaller than in SBC. Thus, a disturbance in thethreshold voltage (e.g. leaking of the stored charge causing a thresholdvoltage drift, interference from operations on neighboring cells, etc.)that may have gone unnoticed in SBC because of the large gap between thetwo states, might cause an MBC cell to move from one state to another,resulting in an erroneous bit. The end result is a lower qualityspecification of MBC cells in terms of data retention time or theendurance of the device to many write/erase cycles. Thus there may beadvantages to using both MBC cells and SBC cells, depending on theapplication's requirements.

While the above explanations deal with floating-gate flash memory cells,there are other types of flash memory technologies. For example, in theNROM flash memory technology there is no conductive floating gate but aninsulating layer trapping the electric charge. The present invention isequally applicable for all flash memory types, even though theexplanations are given in the context of floating-gate technology.

Program Disturb

There are several sources of errors in flash memory devices. Onespecific source of error is typically called “Program Disturb” or “PD”for short. The PD effect causes cells that are not intended to bewritten, to unintentionally move from their initial left-most state tosome other state. (The explanations herein assume the common practice,also used in FIGS. 2A, 2B, and 2C, of drawing the threshold voltage axissuch that its left direction represents lower values. This is anarbitrary practice and should not be construed to limit the scope of theinvention in any way). Referring to the two-bit-per-cell example of FIG.2C, cells that are in the leftmost state corresponding to bit values of“11” (or in other words, to the cell's erased state) and which aresupposed to remain in such state, are found to be in thenext-to-leftmost state of “10”, resulting in one bit out of the two bitsstored in the cell to be incorrect. In some cases, especially in cellsstoring more than two bits per cell and having more than four states, PDeffects might turn out not only as a move from the leftmost state to itsimmediately adjacent state, but also as a move from the leftmost stateto more distant states, and also as a move from a state that is not theleftmost state to another state to its right (i.e. having a higherthreshold voltage). However, the case described first above of movingfrom the leftmost state to its immediately adjacent neighboring state isthe most common, and will be used herein for all examples andexplanations without limiting the generality of the methods of thepresent invention.

The reason for the PD effect is easy to understand when reviewing thevoltages applied to the cells of a NAND flash device when programming apage. When programming a page of cells, a relatively high voltage isapplied to the word line connected to the control gates of the cells ofthe page. What decides whether a certain cell threshold voltage isincreased as a result of this control gate voltage is the voltageapplied to the bit line connected to that cell. Cells that are not to bewritten with data have their bit line connected to a relatively highvoltage level that minimizes the voltage difference across the cell.Cells that are to be written have their bit line connected to lowvoltage, causing a large voltage difference across the cell, andresulting in the cell's threshold voltage getting increased, thus movingthe cell to the right on the voltage axis of FIG. 2C and causing thecell's state to change.

However, even though cells that are not meant to be written have a lowervoltage difference across them than cells that are meant to be written,they still have some voltage difference them. To reduce the voltageacross these non-programmed cells even more, their channels may be“boosted” to a voltage closer in magnitude to the programming voltageapplied to the selected word line, and thereby reduce the voltagedifference across such memory cell devices. This is done by biasingother non-selected word lines in the memory block to an intermediatevoltage closer to the “relatively high” bit line voltage correspondingto the cells that are not meant to be written. This biases the channelof these cells to a higher voltage, which is boosted to an even highervoltage when the selected word line is pulsed to a high programmingvoltage. However, since the charge trapped in the programmed cells alongthe selected word line partially negates the voltage applied to thosenon-selected word lines, and the overall boosting depends on the data(i.e., memory state) programmed to previous cells along the same bitline. For example, cells programmed to the “C” state (i.e., maximumcharge stored in the memory cell) have the highest threshold voltage ofsuch memory cell devices. If other cells along the bit line werepreviously programmed to the “C” state, this reduces the boosted voltagethat is achieved, thus increasing the voltage across the memory devicethat is not to be written, and which causes unintentional programming.

In addition, if the page to be written has some cells that are writtento high threshold voltages (for example, to the rightmost state), thenthe voltage difference across non-programmed cells gets higher. This isbecause all control gates of all cells of the page get the same voltageapplied to them, and the higher the threshold voltage to be reached, thehigher is that voltage. Therefore the need to apply higher control gate(i.e. word line) voltage to some cells, results in higher voltagedifference at the non-programmed cells. Even though the cells aredesigned with the goal of not being effected by such anticipated voltagedifference, in actual NAND flash devices such voltage differences stressthe cells and might result in some of them changing their state eventhough this was neither intended nor desired.

To summarize the above explanation, PD is an effect in which whenprogramming a page of cells, some cells that are intended to remain intheir present memory state end up in another state, resulting in biterrors when reading those cells. Unfortunately, typical real-life userdata is not random. Measurements on real-life user files show that thevarious possible states of the cells do not have equal probability tooccur. As the leftmost state of the cells is the default value of cellsnot being written to, this state is the most frequent. This is easy tounderstand—a section of memory not initialized or not used within afile, very often corresponds to cells in the erased state.

As a result, in real-life applications the problem of PD errors is moresevere than what is expected based on random data patterns statisticalcalculations. Relatively many cells will be in the erased state that isthe most vulnerable state to PD errors, and therefore more PD errorsthan are predicted by random data distribution models will actuallyoccur. The present invention deals with reducing the number of errorsdue to PD effects by manipulating the user data and randomizing theactual sequences of voltage levels or states programmed into the flash.

NAND Flash Concepts Introduction

To better understand the remaining description, several concepts andstructures of an exemplary NAND flash memory device and flash filesystem are now introduced.

A block is the smallest chunk of a NAND flash memory that can be erasedas a single unit. In reference to FIG. 1, the block includes the memorycells associated with the word lines selectable by a pair of blockselect transistors (i.e., the word lines between the corresponding blockselect lines), and the bit lines whose memory cells are coupled to thesesame physical word lines. A physical page is the smallest chunk of aNAND flash memory that can be written (i.e., programmed) as a singleunit. In reference to FIG. 1, a physical page may include all memorycells along a single word line, and more than one physical page maycorrespond to the memory cells of a single word line. For example, in anMBC memory, a single word line may include a lower page and an upperpage, and may further include lower and upper pages corresponding toeven bit lines, and lower and upper pages corresponding to odd bitlines, for a total of four physical pages for each physical word line. Ameta-page is one or more physical pages that are linked together to forma larger page. All physical pages within the meta-page are read/writtenin parallel to achieve higher performance.

An ECC page includes one or more sectors protected by a single clusterof ECC redundancy bytes. For example, in a single-sector ECC page, eachsector is protected by its own ECC redundancy bytes, whereas in an ECCpage having four 512-byte sectors, each 2KB of data information isprotected by a single cluster of ECC redundancy bytes. Each ECC page mayinclude a header of several bytes (e.g., 2, 6, 14, or some other numberof bytes), in addition to the data.

The logical address space (e.g., of the host) is divided into equalsized logical groups of sectors. Each logical group contains exactly thenumber of sectors that will fit in a meta-block. A meta-block is aphysical group of sectors that is erasable as a unit, and can be used tostore a logical group of data. Two sector types are both stored inmeta-blocks: data sectors for storing host data, and control sectors forstoring firmware data. Control sectors are typically not accessed by thehost. At a given time, a given meta-page typically contains only data orcontrol sectors (e.g., except for scratch pad blocks, which may containboth types).

A logical to physical address translation is performed to relate ahost's logical address to a corresponding physical address in flashmemory. The lowest logical sector address (i.e., LBA) of the logicalgroup does not need to be the first sector of the meta-block to which itis mapped. In other words, there may be an offset between the lowestaddress of a logical group and the lowest address of the meta-block towhich it is mapped. A page tag is used to identify any offset, such asidentifying the starting logical sector address of the data stored inthe first physical sector of the meta-block.

The memory management system allows for update of a logical group ofdata by allocating a meta-block dedicated to recording the update dataof the logical group. When the host starts to write data in a logicalgroup, an update block is opened. The update meta-block records updatedata in the order received and has no restriction on whether therecording is in the correct logical order as originally stored(sequential) or not (non-sequential). Initially, such an update block isopened as a sequential update block, but if any of the writes arenon-sequential, the block is converted to a non-sequential (i.e.,“chaotic”) update block. Eventually the update meta-block is closed tofurther recording. One of several processes will take place, but willultimately end up with a fully filled meta-block in the correct orderwhich replaces the original meta-block. In the chaotic case, directorydata is maintained in the non-volatile memory in a manner that isconducive to frequent updates.

Data of a complete logical group of sectors is preferably stored inlogically sequential order in a single meta-block. In this way, theindex to the stored logical sectors is predefined. When the meta-blockhas in store all the sectors of a given logical group in a predefinedorder it is said to be “intact.” As for an update block, when iteventually fills up with update data in logically sequential order, thenthe update block will become an updated intact meta-block that canreadily replace the original meta-block. On the other hand, if theupdate block fills up with update data in a logically different orderfrom that of the intact block, the update block is a non-sequential(i.e., “chaotic”) update block and the out-of-order segments must befurther processed so that eventually the update data of the logicalgroup is stored in the same order as that of the intact block. In thepreferred case, it is in logically sequential order in a singlemeta-block. The further processing involves consolidating the updatedsectors in the update block with unchanged sectors in the original blockinto yet another update meta-block. The consolidated update block willthen be in logically sequential order and can be used to replace theoriginal block. Under some predetermined condition, the consolidationprocess is preceded by one or more compaction processes. The compactionprocess simply re-records the sectors of the chaotic update block into areplacing chaotic update block while eliminating any duplicate logicalsector that has been rendered obsolete by a subsequent update of thesame logical sector.

Mappings between logical groups and physical groups (meta-blocks) arestored in a set of tables and lists distributed among the non-volatileflash memory and RAM within a flash controller. An address table ismaintained in flash memory, containing a meta-block address for everylogical group in the memory system. In addition, logical to physicaladdress records for recently written sectors are temporarily held inRAM. These volatile records can be reconstructed from block lists anddata sector headers in flash memory when the system is initialized afterpower-up. The hierarchy of address records for logical groups includesthe open update block list, the closed update block list in RAM and thegroup address table (GAT) maintained in flash memory.

An open update block list is a list in controller RAM of data updateblocks which are currently open for writing updated host sector data.The entry for a block is moved to the closed update block list when theblock is closed. The closed update block list is a list in controllerRAM of data update blocks which have been closed. A subset of theentries in the list is moved to a sector in the Group Address Tableduring a control write operation.

The Group Address Table (GAT) is a list of meta-block addresses for alllogical groups of host data in the memory system. The GAT contains oneentry for each logical group, ordered sequentially according to logicaladdress. The nth entry in the GAT contains the meta-block address forthe logical group with address “n.” It is preferably a table in flashmemory, comprising a set of sectors (referred to as GAT sectors) withentries defining meta-block addresses for every logical group in thememory system. The GAT sectors are located in one or more dedicatedcontrol blocks (referred to as GAT blocks) in flash memory.

Such flash file system concepts are more fully described in U.S. Pat.No. 7,139,864 to Bennett, et al., the disclosure of which isincorporated herein by reference in its entirety.

Scrambling

From a logical point of view, the data stored in the memory cell arraycan be represented as a two-dimensional (2D) bit map with the bit-lineson one axis and the word-lines on the other. With this in mind,effective data pattern scrambling fundamentally accomplishes two things:(1) manipulate data bits appropriately to alter the programmed patternof memory cell states; and (2) minimize the alignment of memory cellsprogrammed to the same states from word-line to word-line, and also frombit-line to bit-line.

FIGS. 3A and 3B depict conceptual block diagrams for an exemplary DataPattern Scrambler 150 and Descrambler 170, respectively, also referredto herein simply as a Scrambler. Such a Scrambler is based on a simpleencryption method using exclusive-OR (XOR) logic and a known key. Thesimple XOR logic provides for scrambling data using the key, and thendescrambling to get the original data back using the same key. In FIG.3A, unscrambled data from a host is conveyed on bus 152 to an XOR block156. In addition, a scrambling key is conveyed on bus 154 to the XORblock 156, which then performs a bit-wise XOR operation to generate thescrambled data conveyed on bus 158. The key generator 168 receives aclock signal 160, a seed key on bus 162, and a starting key number SKNon bus 164 (explained below), from which it generates the scrambling keyon bus 154. In FIG. 3B, scrambled data from memory is conveyed on bus172 to an XOR block 176. The scrambling key is conveyed on bus 174 tothe XOR block 176, which then performs a bit-wise XOR operation togenerate the unscrambled data conveyed on bus 178. As before, the keygenerator 188 receives a clock signal 180, a seed key on bus 182, and astarting key number SKN on bus 184, from which it generates thedescrambling key on bus 174. Even though shown as separate blocks, theXOR block and Key generator block may be shared and used for bothscrambling and descrambling, with appropriate steering of the variousinput and output busses. Bit-wise XOR operation between Host data andScrambler Keys enables simple descrambling with the known Seed and Keynumber used to scramble.

Consequently, the core of the Scrambler 150 and Descrambler 170essentially becomes the generations of the Keys. Instead of regardingKeys as numbers, such keys may be viewed as strings of 1's and 0's.Controlling the bit ordering and the number of 1's and 0's in thestrings is one of the underlying principles to generating suitableScrambling Keys.

A set of bit strings can be easily generated by rotating an initial bitstring, refer to as the Seed, one bit at a time until the pattern ofbits starts repeating. This can be accomplished by employing a fixedlength shift register to create a sequence of rotating Keys with the Keyvalues being controlled by the initial Seed value. For example, an 8-bitshift register can produce up to 8 unique Keys. An exemplary set ofrotating 8-bit keys (left direction) are shown in FIG. 4. In thisexample, Key0 is followed by Key1, which is followed by Key2, etc. Ofcourse, an initial bit string alternatively could be rotated to theright to generate a sequence of rotating keys. In some embodiments, aserial shifter may be used, while in other embodiments other shifters,such as a barrel shifter, may be used.

Referring now to FIG. 5, an exemplary set of rotating 32-bit keys areshown, which are rotated to the left to produce 32 distinct scramblingkeys. The initial key, Key0, takes on the value of the seed key, whichis 0×695334C6. Other seed keys are contemplated, and may be empiricallydetermined. The seed key preferably provides a good amount of“randomness” of its bit pattern, and also preferably balances the numberof 1's and 0's in the key. Each successive key is generated by asingle-bit left rotation of the preceding key. For example, Key1 isgenerated by left-shifting Key0 by one bit position. The 32 differentkey are also numbered, as shown in the table, and a given key numberrepresents the seed key rotated by a number of bits equal to the keynumber. For example, Key21 represents the seed key, Key0, rotated by 21bits to the left. This key may be generated by single-bit rotating theseed key 21 times (e.g., once per clock), or may be generated in asingle clock cycle using a barrel shifter, or possible by othertechniques.

Thus, in certain embodiments, the Scrambler Key may be generated from aninitial Seed Key which may be rotated one bit at a time to createsuccessive Scrambler Keys. The Seed preferably is a minimum of 32 bitslong (although any other length may also be used), and preferably has apredetermined hardware default value, which firmware (FW) may changeduring initialization (as further described below). Every 32 bits ofdata are XOR'ed with a Scrambler Key, after which the next Key isautomatically generated (e.g., by left-rotating the current Key tocreate the next Key) to be used with the next 32 bits of data. Only theSeed, which is the initial Key, needs to be set by the FW becausesubsequent Keys are automatically generated for each new cycle (e.g., bytoggling the CLK signal shown in FIGS. 3A and 3B).

The Keys are logically XOR'ed with chunks of data (e.g., 32 bits ofdata), thus the number of 1's and 0's in the Keys causes data bits totoggle, which directly translates to memory cell states being scrambledacross the word-lines. After 128 bytes (32 Keys*32 bits/8 bits/byte)from the beginning of the memory page, the key number will wrap aroundand the scrambling pattern will repeat itself. This is visually depictedin FIG. 6, which shows several memory pages 208, 216, 224, etc. of amemory block 200. The first 32-bit word (labeled 202) of the firstmemory page 208 is scrambled using Key0. As additional words in the page208 are written, the key number is incremented as shown, so that thethirty-second word (labeled 204) is scrambled using Key31. The next wordwritten (labeled 206) is scrambled using Key0, as the 32-keys are reusedfor each subsequent group of 32 words in the page. Since the purpose ofthe Scrambler is to avoid fixed patterns rather than to encrypt thedata, re-using the keys after 128 bytes is sufficient “randomness” tobreak up memory cell states across a word line (i.e., from bit line tobit line). However, other randomization techniques may be employed, asnoted below, that may be even more “random.”

To break up memory cell states going down the bit-lines, each pagestarts using a different key. The first 32-bit word (labeled 210) of thenext memory page 216 is scrambled using Key1. As additional words in thepage 216 are written (or read), the key number is incremented, asbefore, so that the thirty-first word (labeled 212) is scrambled usingKey31, and the thirty-second word (labeled 214) is scrambled using Key0.The subsequent word 215 scrambled using Key 1 since, as before, the 32different keys are reused for each subsequent group of 32 words in thepage.

The identification of the first key to be used for each page may beprovided by a Starting Key Number (SKN), which acts as an index oroffset from a fixed reference point (i.e., Key0 or the Seed). The indexis changed on every logical page transition to create a staggered bitpattern produced from the bit strings of the rotating Keys. Such alogical page address transition occurs when transitioning from one wordline to the next word line, and may also occur within a single word line(e.g., in an MLC cell having an upper page and a lower page stored inthe memory cells of a given word line, and also if a word line has morememory cells than the number of bits in a page). The ability to offsetthe starting Key results in a bitmap-like pattern of walking 0's and 1'sthat when XOR'ed with the data, produces a striping effect across thememory cell array. Thus, the Scrambler Keys serve the purpose oftoggling bits. The rotation of the Keys serves to shift the bit patternsacross the word lines (and across different pages). The Starting KeyNumber serves the purpose of shifting the bit patterns going down thebit-lines, while setting the correct Key according to the appropriatepage.

To help determine which Key should be used for a given byte within apage (i.e., along a word line), we introduce a D-Word Offset Number,which counts from 0 to 31, starting with the first word of a page, thenrepeats for subsequent groups of 32 words. In other words, the D-WordOffset Number counts from 0 to 31 over and over, and indicates which keyto use, relative to the first key in the page (which may be Key0, as inpage 208, or another initial key, as shown in the other pages 216, 224,etc.) This D-Word Offset Number is derived from the Column Offset of thefirst sector to be accessed within a physical page, and may becalculated by the following formula:

${D - \text{word~~offset}} = {{round\_ down}\lbrack {{{mod}( \frac{Column\_ Start}{\begin{matrix}{{Key\_ Length}\mspace{14mu}( {= 4} )} \\{{{No}.\mspace{14mu}{of}}\mspace{14mu}{keys}\mspace{14mu}( {= 32} )}\end{matrix}} )},0} \rbrack}$Column_Start is the first data byte, including header and data bytes(but excluding ECC bytes unless such ECC bytes are also scrambled) inthe physical page from which we start reading or to which we startwriting. It is calculated by the sum of the header length (e.g., 6bytes, 14 bytes, or other suitable value)+data field length (e.g., 512bytes, 2048 bytes, or other suitable value) of all the previous sectors(or, for some embodiments, ECC pages) in the physical page. TheKey_Length is the length, in bytes, of each Scrambling Key. The “mod”function (i.e., “modulo” function) returns the remainder of the firstargument divided by the second argument, while the “round_down” functionreturns the first argument rounded to the number of digits indicated bythe second argument. Since here the indicated number of digits is 0, thefunction rounds down to an integer. A numeric example is described belowin relation to FIG. 10.

The D-Word Offset is typically set to zero for the first sector of eachpage, but is typically not zero for the other sectors in the physicalpage, since the sector lengths are frequently are not an even multipleof 128 bytes (i.e., 4-byte keys, times 32 keys=128 bytes). All pagespreferably start with a zero column offset regardless of the meta-pageconfiguration (i.e., the number of physical pages in the meta-page).

As described above, the SKN may be viewed as indicating which of the 32keys should be used for the first word in the physical page. In someembodiments, the SKN may be calculated by taking the lower 5 bits of thesum of the Page Offset Number and the D-Word Offset Number, as shown inthe following equation:SKN=mod[(SKN Page Offset+SKN D. Word Offset),32]The Page Offset Number is preferably set to either the lowest 5 bits ofthe physical page address within the block or the lowest 5 bits of thelogical page address within the block. This relationship may be seen inFIG. 6 by observing, for example, that the SKN of the first sectorwithin each page (where D-Word Offset=0) is identical to the Page Offsetnumber. If the size of each sector within a page is an even multiple of128 bytes, then each sector would start with the same SKN. However,frequently sector sizes are chosen such that each sector within a pagehas a different SKN.

For certain sector sizes that are not an even multiple of 4 bytes, thefirst byte of a new sector may fall within a 32-bit word (and thuswithin a 32-bit Scrambling Key). We introduce a Byte Offset number toindicate the starting byte position within a given 32-bit Scrambler Key.This is necessary to address keys spanning across sector boundaries (oralternatively, across ECC page boundaries), which is an importantconsideration in determining the correct SKN when performing a memoryread with a non-zero column offset (i.e. starting read in the middle ofa memory page). The byte offset is typically set to zero for the firstsector of each page. The byte offset for other sectors depends on thesector size (or ECC page size), excluding ECC, and sector number or ECCpage number. The Byte Offset number may be calculated by the followingformula:Byte offset=mod(Column_Start,Key_Length(=4))As before, the Column_Start is the first data byte (including header anddata bytes, excluding ECC bytes) in the physical page from which westart reading or to which we start writing. Thus, the Byte Offset countsfrom 0 to 3 over and over for increasing Column_Start values. Saiddifferently, the Byte Offset value indicates which of the four bytes ofa Scrambling Key corresponds to a given byte within a physical page.

A Byte Offset Number example with 32-bit Keys is shown in FIG. 7. Thefirst sector, Sector 0, is 518 bytes long (reflecting, for example, a6-byte header and a 512-byte data portion). Since this is not an evenmultiple of 4 bytes, this sector ends in the middle of a ScramblingKey1. (Recall from FIG. 6 that byte 512 corresponds to the first byte inKey0, since this byte is an even multiple of 128 bytes.) The first bytein Sector 1 corresponds to byte 2 within Key1. Sector 1 thus begins witha Byte Offset value=2, and a D-Word Offset value=1. This may be seen inFIG. 8, which shows the SKN calculation for a page including 16 sectors.The first two pages are indicated in the table, corresponding to PageOffset Values of 0 and 1. The first sector in each page includes a6-byte header, and additional sectors within each page each include a2-byte header. The first two lines of this table correspond to theexample graphically shown in FIG. 7. In particular, the second lineindicates a D-Word Offset value=1, and a Byte Offset value=2. It mayalso be appreciated that the SKN of sectors within a given page are notall the same, as described above. Moreover, the SKN of the first sectorof each page is identical to the Page Offset number, as described above.

In certain other embodiments, subsequent Scrambler Keys may be generatedin other ways than a simple single-bit rotation of a starting key, toimprove the “randomness” of the scrambling keys. For example, eachsubsequent key may be derived from an initial number or Seed which isrotated multiple times to create additional Scrambler Keys. After eachXOR operation, the next key number is calculated (e.g., calculating byhow many bits to left-rotate the key) and the key is rotatedaccordingly. By so doing, the Scrambling Keys are less repetitive, andthus XOR the data with a more random-like data pattern than isachievable using a simple single-bit rotation. An exemplary calculatedkey sequence of 8-bit keys is shown in FIG. 9. Each Scrambling Key is aleft rotation of the original seed by the Key Number, i.e. Key6 is theseed Key0 left-rotated by 6 bits, but as shown, each subsequent key isnot merely a single bit shift of the previous key. In this example, Key0is followed by Key6, which is followed by Key3, etc.

As before, however, 32-bit keys (or larger) are more suitable than 8-bitkeys. In such an example, the Starting Key Number (SKN) may berecursively calculated according to the following formulas:K_(n)=seed rotated left by SKN_(n)SKN_(n+1)=[SKN_(n)+C+P+(SKN_(n)+P)]>>5Where;

-   -   C=DWord Offset & 0×1f    -   P=Page Offset Number & 0×1f    -   SKN₀=P

The Page Offset Number, the D-word offset number, and the Byte OffsetNumber are calculated as before, using the formulas shown above. The“>>” operator is a right non-circular shift function, resulting here ina “divide by 32 without remainder” function. The “&” operator is abit-wise AND operator. An example illustrating the calculation of theD-Word Offset Number and the Byte Offset Number, for a memory having2062-byte ECC pages, is shown in FIG. 10. Each ECC page includes a14-byte header and four 512-byte sectors, for a total of 2062 bytes.

A partial page may be accessed without necessarily accessing the entirepage. Setting the SKN and calculating the correct Key provides forcorrect reading or writing from any sector in the Card without having toread/write any additional sectors to set the scrambling Key. Preferably,the FW sets the Starting Key Number and configures the Scramblerappropriately for scrambling/descrambling starting at any ECC page inthe memory card. As further explained below, the SKN is set at thebeginning of each chunk according to either the logical block address(LBA) address or the physical location of the first sector to bewritten/read. The FW sets the SKN in addition to setting the Page OffsetNumber, the D-Word Offset number and the Byte Offset Number registers.After setting the SKN, the key generator (e.g., hardware, or firmware)can calculate the correct scrambling Key for the particular sector thatis about to be read or written.

Whenever an operation starts in the middle of a page, the Page Offset,D-Word Offset, and the Byte Offset registers may be set by FW accordingto the table shown in FIG. 11. This table reflects the example,introduced above, of 2062-byte ECC pages each including four sectorspreceded by a 14-byte header, and other sizes are, of course, clearlycontemplated. The D-Word Offset and the Byte Offset registers arepreferably cleared when setting the Page Offset register (since mostreads and writes start at the beginning of a page), so they should beset after the Page Offset Register is set. After these registers areset, FW can then set the SKN value according to the table shown in FIG.12. Such a table is preferably hard-coded in the FW so that an SKN maybe quickly determined without having to perform the recursivecalculation for each memory access. Alternatively, the table may becreated by the FW during initialization by recursively calculating thecorresponding SKN for each of the four ECC pages within each of thethirty-two physical pages (i.e., corresponding to each value of the PageOffset Number). By doing the lengthy recursive calculations once, andsaving the table, the FW can quickly determine an SKN without having toperform the recursive calculation for each memory access.

Whenever a sequential operation (read/write) crosses a page boundary andis about to access the next page, the SKN has to be adjusted to that ofthe next page. Setting the Key value at a physical page crossing withina meta-page (such as at plane or die boundary) is preferably done byhardware (HW), by manually clearing the D-Word Offset and the ByteOffset Registers while keeping the Page Offset value as it is. Settingthe Key value at a meta-page crossing is preferably done automaticallyby HW when directed by FW by writing a ‘1’ in the Page increment bit ofan SKN Auto Increment Register, which will initiate the key adjustment.The Auto Page Increment bit is preferably set between meta-pagetransactions, and preferably is automatically cleared after the Keyadjustment by HW.

Within a memory system or controller, the Scrambler may be placedbetween the buffer management unit (BMU) and the Flash interface (+ECC).During write transfers, the scrambling can occur after multiplexing thefill pattern data, which allows the fill data to be scrambled as well.ECC check bit generation may be performed after scrambling (on thescrambled data), and need not pass through the Scrambler. There is noissue here, as the ECC bits themselves are already random, so there isno need to scramble them again. Also, given the data structure design,duplicate sector data patterns (including the header) will rarely berepeated on consecutive pages.

During read transfers, descrambling occurs after the mis-comparisoncounting (which may be employed to also detect “erased” sectors and “badblock” markers, as noted below). ECC error detection may be performedprior to descrambling, but correction is preferably performed after suchdescrambling. This eliminates the need to buffer the entire sector inorder to correct any ECC bits before descrambling, and thus eliminatesany performance impact due to such additional buffering. This ispossible since any FCC errors in the original data stream should notaffect the unscrambled data stream beyond the individual bits which arein error, as there is no feedback mechanism between the data and thegeneration of the next key.

Support for On-Chip Copy Functions

The Page Tag feature enables intact blocks to begin with any givenlogical page. i.e., any LBA can be written to any given physical pagewithin the block, according to the Page Tag value. On-Chip Copyfunctions enable copying data between different blocks of the same diewithout fully passing the data through the Controller. Since theScrambler resides outside of the NAND, On-Chip Copy necessarily impliesthat the data is copied intact (i.e., without being de-scrambled andthen re-scrambled). Consequently, the same scrambling key will be usedfor the same logical page address, regardless of the physical pages theyare written to.

Support for on-chip copy (OCC) is achieved through setting the PageOffset Number Register based on the logical address rather than thephysical address (at least for most block types). As noted below, thePage Offset Number Register for some block types (e.g., control blocks)may remain based on the physical address.

Logical Page Calculation

Similarly to the way a meta-block is divided into physical meta-pages, aLogical Group can be divided into Logical Pages. Each Logical Page hasthe same size as one meta-page, and there are as many Logical Pages in aLogical Group as there are meta-pages in a meta-block. The Logical PageAddress (i.e., Logical Page value) may be determined from the LBA valueby first dividing the LBA value by the meta-page size. If there are only32 different keys (32 bits), we then take only the lower 5 bits, asdescribed by the following formula:

${{Logical}\mspace{14mu}{Page}} = {{mod}( {{{RoundDown}( {\frac{LBA}{{meta}\text{-}{page}\mspace{14mu}{size}},0} )},32} )}$All the sectors within a meta-page have the same Logical Page value,which is also described herein as the Logical Page Offset value. Thespecific scrambling key of each sector is different, since the D-WordOffset and Byte Offset registers have different values according to thesector offset within the page, as explained above.Initialization

During initialization the FW scans the blocks in the Open Block List todetermine what the last state of the card was prior to the power cycle.The block type (i.e., control, data, etc.) is determined according tothe ID byte in the header (as further described below), and the OpenUpdate Block List is built through scanning the headers and reading theLBAs of the sectors written in the open blocks. During initializationand prior to building the Open Update Block List, the stored data ispreferably entirely scrambled. This situation creates a Chicken-and-Eggproblem in that reading must be performed to determine the LBAs of eachsector, but in order to properly read the content of each sector, theLogical Page address (which is based on the LBA) is required to properlyset the descrambling Key to unscramble the data. The resolution to thisinitialization dilemma is to store scrambling key information (i.e. theSKN Page Offset Number, or other information from which the scramblingkey may be determined) in the scrambled sector headers and then extractit during card initialization.

After the initialization is completed there is no need to extract theSKN from the header, as the FW knows the location, the block type andthe Page Offset Register value of each sector in the card. Therefore,the FW can set the Scrambler Registers correctly, then the HW can readand descramble the data as if the Scrambler is transparent to the FW.

Storing the Scrambling Key Information in the Header

The page headers preferably include a 5-bit field (or other appropriatelength) for the Page Offset Number (or other scrambling key information)that is used to determine the scrambling key for scrambling the data forthe given page. Many different arrangements are possible, including theheader format indicated in FIG. 13, which includes a 6-byte LBA/controlheader for the first sector in a page and a 2-byte header for the restof the sectors, and which is suitable for single-sector ECC pages (i.e.,each sector protected by its own ECC redundancy bytes). The 2-byteheader is the same as the 6-byte header, except without the first 4bytes, as the LBA need only be stored in the first sector of the page.The Data Structure ID field (also referred to herein as a Sector IDfield) may be used to identify what kind of sector it is (e.g., control,data, etc.). The Application Byte field is reserved for use byindividual applications.

In certain embodiments it may be desirable to provide for a larger pagesize. For example, the ECC page size may be 4 sectors long (i.e., each2KB of user data information is protected by a single cluster of ECCredundancy bytes) and each ECC page may have a single header of 14bytes, as shown in FIG. 14, including a 2-byte sector header for each ofthe four sectors, and the LBA of the page. Each 2-byte Sector Headerincludes a Page Offset field, which is used to determine which PageOffset Number was used to scramble the data for the given page.

Since the header itself is preferably scrambled, along with the data inthe rest of the sector, the actual Page Offset value is not directlywritten into the header. Instead, a Page Code is written by the FW intothe header, which is then scrambled (i.e., by HW) to generate a MappedPage Offset Code which is actually written into the memory page. Anexemplary page offset mapping table is shown in FIG. 15, whichcorresponds to a Seed of ×69C734C6. Other mapping tables are alsopossible for this same default seed, and different mapping tables forother default Seeds, but conceptually such tables will be similar tothis table. The first column of this table is the Page Offset value(ranging from 0 to 31 since there are 32 keys). The second column listsa corresponding Page Code, which is the value written into the memorypage by the FW. Since the scrambling key for a page is dependent uponthe Page Offset value, each page will be scrambled differently. For thisexample, since the 5-bit Page Offset field for Sector 0 corresponds tobit positions 11-15 of the first word in Sector 0, each written PageCode is scrambled by bits 11-15 of the corresponding Scrambling Key forthe particular page (shown in the third column), to generate the MappedPage Offset Code shown in the fourth column.

This lookup table provides a 1-to-1 mapping between the Page Offsetvalue and a Page Code that can be written by the FW and scrambled andstored in the memory page. A reverse mapping table, shown at the rightside of FIG. 15, provides a 1-to-1 mapping between the scrambled 5-bitvalue actually stored in the header and read with the scramblerdisabled, and the corresponding unscrambled Page Offset value (i.e., theSKN value for the first sector in a page). Such lookup tables are basedon the particular Seed chosen, and are preferably stored by the FW inRAM to provide fast mapping during a write, and quick determination ofthe SKN after reading the scrambled header.

During write commands, the FW knows the logical address, the targetphysical location and the block type of the write command. Therefore,the FW knows the Page Offset value, whether it's based on a Logical Pageor a Physical Page (e.g., such as for a control block, as describedelsewhere herein). As part of every write command, the FW can look upthe Page Offset value in the Page Offset Mapping table and write the5-bit Page Code from the table into the Page Offset field in the header.Those 5 bits will be scrambled (e.g., by HW), along with the data in thepage, and no special handling is needed. After scrambling, each one ofthe 5-bit Mapped Page Offset Code combinations will have a distinctvalue, which may be used to uniquely identify the Page Offset valueduring initialization.

Extracting the SKN from the Header

During initialization, the header may be read with the Scramblerbypassed, since the Key is still unknown. Since the entire header itselfis preferably scrambled, the Page Offset Number cannot simply be readwith the scrambler disabled. Instead, the Mapped Page Offset Code isread, and the Page Offset value is determined, such as by using thereverse mapping lookup table of FIG. 15, and the scrambling Key iscalculated. Since only the headers at the beginning of each meta-pageneed be read during initialization, the Page Offset extracted from the5-bit header field corresponds to the final SKN value, because theD-Word Offset and the Byte Offset are both equal to zero. Such tablesalternatively may be replaced by a translation function. Use of suchtables guarantees a 1:1 mapping between the Page Offset value and the5-bits field actually written in the header.

Once the SKN is known, the FW can calculate the Scrambling key by leftrotating the Scrambling Seed by SKN places to the left. Once the key isknown, the FW can XOR the header data with the scrambling key andresolve the header information. An alternative is to enable thescrambler, set the Scrambler Registers, and re-read the sector using theScrambler circuitry to de-scramble the data, but since the header isusually only several bytes long (e.g., 6 bytes, 14 bytes, etc.), merelyXOR'ing the data in FW may be much simpler and faster. When descramblingin FW, the FW has to calculate the rotation of the Key (or shift theKey, as appropriate) after each XOR operation as described above.

The tables shown in FIG. 15 refer only to the first ECC page within thephysical page, as the scrambling keys, and hence the values written tothe flash, are different for other ECC pages within the physical page.This is shown, for the exemplary embodiment thus far described, by thetable depicted in FIG. 16. This table shows the SKN value for each ofthe four ECC pages in a physical page, for each of the thirty-two PageOffset values. The table also shows the Column_Start value, D-WordOffset value, and Byte Offset value for each byte position in the entirephysical page, and the corresponding SKN. This is another table that ispreferably built by FW upon initialization to speed determination of theSKN operation, especially for memory reads and writes that do not startat the beginning of a page, and is particularly helpful if the SKN iscalculated recursively, such as described above.

Page Offset Number in Sequential Update Blocks/Intact Blocks

Sequential Update Blocks, or Intact Blocks, set the Page Tag offsetparameter at the very first write to the block. It is determined by theoffset of the first logical page that is written to the Update Blockwithin its corresponding logical group. A logical page may be a set ofcontiguous sectors which are written to one full meta-page, i.e. it hasthe size of a meta-page and it is aligned to meta-page boundaries. Oncethe Page Tag parameter is set, all the logical pages written in theUpdate Block are written sequentially from the first page, and eachlogical page will have the same offset relative to the physical pages inwhich it is written.

In order to make the scrambling key independent of the Page Tag value,the Page Offset Number Register setting is determined according to theLogical Page value, rather than the Physical Page value. In the eventthe Page Tag is zero, the two values coincide.

Page Offset Number in Chaotic Update Blocks

A block written in non-sequential sector order is known as a ChaoticUpdate Block. Similarly to the Sequential Update Blocks, Chaotic UpdateBlocks also use the Logical Page as the Page Offset Number, thusenabling the use of the on-chip copy functions. The issue here is thatsince the same page can be written over and over to the same block, allthe pages may use the same scrambling key, resulting in a repeatingpattern throughout the block. This potential issue may be averted byusing only the lower memory page for Chaotic Update Blocks (i.e., onlywriting 2 of the 4 MLC states per memory cell, thus treating the blockas a binary block) to mitigate the boosting effect that results from therepetitive pattern, and thus avoid the program disturb phenomenon. Ascan be seen in FIG. 2C, the improved margins are achieved because thedifference in threshold voltage between the two states when writing onlythe lower page is greater than if writing both the lower and upperpages.

Page Offset Number in Control Blocks and Scratch Pad Blocks

Control blocks don't use on-chip copy, since they are mainly accessed ona single sector basis. Therefore, the Physical Page is preferably usedas the Page Offset Number, so that each page is scrambled with a Keycorresponding to the physical page number that it was written to. Thecontinually-changing page number will guarantee that a differentscrambling Key will be used as additional pages get written down theblock and thus avoid the occurrence of the worst case patterns whichcause the PD issues. In addition, such control blocks may also use onlythe lower memory page to increase the signal margins of the memorycells.

Scrambling Data in File System Blocks

All control blocks are preferably scrambled, including the Boot Blockand the firmware (FW) blocks (which are included within the file systemblocks). In an exemplary Flash File System, the Boot Block is scannedand read by the FW to find the pointers to the File System Blocks, whichare also partially read by the FW. Since both the Boot Block and theFile System Blocks are scrambled when written, the FW must be able todescramble the data. Only the functionality needed for page read(+descrambling) has to be supported by the FW. Specifically the FWshould support setting the various registers that load the Seed, andspecifying which descrambling Key to use.

The first page in the Boot Block, which holds information regarding themeta-block geometry, the ECC level, and the device ID information,preferably includes the Scrambler Seed that was used to scramble theBoot Blocks and the File System Blocks. The first page itself, however,is preferably scrambled using the default Scrambler Seed which isincorporated in the HW. At the beginning of the initialization process,the first page is read using the default Seed. The Seed which is usedfor the rest of the card is then read from the first page and loadedinto the Scrambler, and used for all subsequent operations. Theremaining pages in the boot block are scrambled with a Page OffsetRegister which is set according to the physical page value (like othercontrol blocks). The FW should include the functionality to set theregisters according to the physical page offset. For proper Scrambleroperation, one should explicitly set the Seed in the Boot Block even ifit is the same value as the default Seed. A Seed value of 0 willessentially cause data to not be scrambled even though the Scrambler isenabled.

Bad Block Detection

Generally Bad Block detection may be done with the Scrambler bypassed.At first download there is no issue, as none of the blocks holds anyinformation. In subsequent downloads, after the card already has someinformation written, it is possible that scrambled data might bemisinterpreted as a bad block. Since the bad block marking is differentfor different vendors, a different detection scheme may need to be usedfor each vendor.

Some vendors mark factory bad blocks by writing zeros to the entireblock. Using the scrambling keys as described above (i.e., the defaultkey value of 0×69C734C6) there cannot be any header combination thatafter scrambling will result in a “00” value in all of the header bytes(e.g., in the LBA and the data structure ID) and will be stored in thefirst sectors in the page. Generally, the header should be designed sothat after scrambling there is no possibility that all header bytes canbe “00.” Therefore, a detection scheme which looks for the “00” patternin the header may be used. Such detection may be easily accomplishedwith the Scrambler bypassed.

Other vendors mark factory bad blocks by writing a single byte in theuser data area (i.e. within the 512 data bytes of a sector, as opposedto the header area or ECC) with any pattern which is not ‘FF’. Thespecific location of the byte changes with the memory type. Big Block(i.e., each page includes more than one sector) MBC memories frequentlymark the block as bad by writing a non-FF pattern to byte 2048 of thelast page. Big Block BIN memories (i.e., single bit per cell) mark theblock as bad by writing a non-FF pattern to byte 2048 of either thefirst or second pages.

Since the byte which is used for the bad block marking can have a non-FFvalue after scrambling, it may be accidentally detected as a bad block,as the scrambled data structure ID will also be unrecognized. However,the mis-comparison counting block of the ECC engine may be used todifferentiate between factory bad blocks and good blocks, since the ECCengine will indicate an uncorrectable ECC error (i.e., UECC) when allbits are either all zeros or all “FF”s.

During detection the Scrambler is bypassed, and the ECC engine isenabled. If the sector holding the bad block marking is readsuccessfully, the block is detected as a good block, regardless of thevalue of the bad block marking byte. A sector is read successfully if itresults in no UECC or correctable ECC. If reading the sector which holdsthe bad block marking will result in UECC, and the value of the badblock marking byte is not all “FF”, the block is suspected as a badblock. In this case, page 0 of the suspect block is then read. If allsectors in page 0 also result in UECC, the block will be determined asbad. If any sectors in page 0 are read successfully, the block willinstead be determined to be a good block. This, of course, representsbut one of many possible methods for bad block detection.

Exemplary Implementation

The above techniques may be carried out in many different specificimplementations. An exemplary operating flow diagram which implementsthe Scrambler functionality described above is shown in FIG. 17. Anexemplary module is shown in FIG. 18 and will now be described. Such aScrambler module is suitable for an ASIC implementation, and preferablyis a self-contained hardware block in order to allow easy integration(or removal) among various ASIC projects with no dependencies to the CPUtype or on any specific ASIC Design Architectures.

The Scrambler hardware block may be placed directly in the data path. Asnoted above, the ECC bytes may be scrambled along with the header anduser data, in which case the Scrambler block should logically be placedat the end of the data path going to the memory interface. However,since it is not necessary to scramble the ECC bits, the Scrambler may beplaced earlier in the data path. A single clock source is sufficient forthe Scrambler module. The clock frequency is preferably no less than thebus speed at which the Scrambler module is clocked.

A Data Input bus and Data Output bus of for example, 32-bits providesfor streaming data through the Scrambler, although such port sizes maybe limited by an internal ASIC bus to 16-bits. A dedicated 16-bitControl Data Input bus provides access to the control registers. A 5-bitInput Address bus is included for addressing control registers and tolatch in the Starting Key Number during HW Flow Control operation.

A set of control lines is preferably included for accessing internalcontrol registers and for HW Flow control. A Reset line may be assertedto reset the Scrambler Module to an initial state and set up for HW Flowoperation. A Read/Write (R/W) control signal is provided to controlregister accesses through Control_Data_In[15:0]. In addition, aControl_SEL line is provided to select between Control Register Accessand HW Flow Control modes of operation. Default selection is preferablyset to HW Flow Control.

The Scrambler Module includes several registers, including a SeedRegister, a Configuration Register, a SKN Page Offset Register, and aSKN Sector Offset Register. The Seed Register is preferably a 32-bit R/Wregister for storing the Initial Key or Key 0, which is the same as theSeed. The default key may be 0×69C734C6, or another suitable value. Inaddition, a control register is provided to trigger loading of thestored Seed Register value into the Shifter. The Seed Register valuedoes not change on reset.

In addition, a Configuration Register is included to control operationof the Scrambler Module. For example, such control includes whether toenable or disable Shifter continuous rotation. Preferably the defaultsetting is to enable continuous shifter rotation. Disabling rotationforces the use of the same key for the entire memory page (i.e. Keys maybe rotated by pre-clocking). The configuration register can also controlwhether to enable full bypass of the scrambling function, resulting indata flow through the module with no manipulation of the data, withminimal delays, and with minimal power consumption. Preferably thedefault setting is to enable full bypass.

The SKN Page Offset Register is preferably a 5-bit R/W register forstoring the Starting Key Number (e.g., assuming 32 different keys). Thedefault value preferably is 0 (i.e. Key0). In Control Register Accessmode, the register value preferably goes back to the default value uponreset. In HW Flow Control mode, the register value is loaded from theAddress Input port on reset. The value loaded into the SKN Register isbased on the memory page address corresponding to the lower 5 bits ofeither the physical page address or the logical page address.

The D-Word Offset Number (e.g., 5-bit value) and the Byte Offset Number(e.g., 2-bit value) may be stored in separate registers, but may insteadbe conveniently combined in a single 7-bit R/W register, which we cancall the SKN Sector Offset Register. This SKN Sector Offset Register maybe viewed as storing the offset from the Starting Key Number. Thedefault value preferably is 0. Regardless of operation mode, theregister value preferably reverts to the default value on reset.

As noted above, this 7-bit register may include two fields based on keysizes of 32 bits, as noted in the following Table 1:

TABLE 1 Exemplary Sector Offset Register Format for 32-bit Keys 6 5 4 32 1 0 D_Word Offset Byte Offset Number Number

The SKN Sector Offset Register bits [6:0] directly correspond to eitherthe memory column address [6:0] or the relative 7-bit byte offset fromthe start of the logical page (also referred to above as Column_Startvalue). The 5-bit D-Word Offset Number indicates the offset key numberthat corresponds to the first byte of the starting sector to bescrambled/descrambled. The D-Word Offset number is relative to the SKNso a value of 0 corresponds to Sector 0 accesses.

The 2-bit Byte Offset Number indicates the starting byte position withinone Key. This is necessary to address Keys spanning across sectorboundaries, which is an important consideration in determining thecorrect SKN when performing a memory read with a non-zero column offset(i.e. starting read in the middle of a memory page). The Byte Offset is0 for Sector0 of each page. The Byte Offset for other sectors depends onthe sector size, sector number, and key size in bytes. Examples ofD-Word Offset Number and Byte Offset Number based on 32-bit Keys areshown above in regards to FIGS. 7, 8, 10, and 11.

Also internal to the Scrambler Module, a parallel-in/parallel-out shiftregister or similar circuit is preferably designed that can rotate bitsin a constant left direction. The bits shifted out one end circularlyreturn on the other end. A fixed size (e.g., 32 bits) allows easiersystem implementation to decode the Starting Key Number for memory readwith column offsets (see discussion of SKN Page Offset Register). Thesize also determines the number of Keys available.

On reset, the shift register preferably automatically reloads the Seedand loads the Starting Key Number. It should also allow loading of theinitial Key from the Seed Register, and may allow pre-clocking based ona count stored in the SKN Registers. Such a pre-clock count may be basedon both the Page Offset Number and the Sector Offset Number stored inthe SKN Page Offset Register and the SKN Sector Offset Register,respectively. Using a shift register has inherent latencies, especiallywith the concept of pre-clocking. These may be addressed by pre-clockingearly before data arrival, using a faster clock, and/or utilizing afaster type of shift register such as a barrel-shifter.

The Scrambler Module also includes an XOR circuit having two input portsand one output port, each of up to 32-bit widths forparallel-in/parallel-out operation. One input port is connected to theData Input port, and the other input port is connected to the Shifteroutput. The single output port is connected to the Data Output port.

Under HW Flow Control, the full Scrambler operation may be controlledusing only the Clock, Reset, and Address[4:0], with no register accessrequired. This is a typical operating mode once the Scrambler registersare configured. Basic scrambling operation may be accomplished, forexample, in the following manner. Initially, the Scrambler configurationregisters are set up and then switched to HW Flow Control mode. Theinitial 5-bit memory page address to be accessed is presented on theAddress Input bus. Then, on asserting a RST pulse, the Page Starting KeyNumber Register is loaded from the Address Input bus, and the Seed(i.e., the contents from the Seed Register) is loaded into the Shifter.On Clock transitions, the Scrambler pumps the unscrambled data from theData Input port, scrambles the data, and outputs the scrambled data tothe Data Output port, and continuously operates in this manner until theconfiguration is changed with Reset. In some embodiments a number ofclock transitions may also be required to pre-clock a bit-serial shifterin order to calculate the correct scrambling keys for use by thescrambler. The general operation is identical for unscrambling.

Generally, the Scrambler Module is initialized for memory accessesaligned to the beginning of a memory page. This is a typical mode ofoperation and requires minimal FW control to (1) enable HW Flow Controloperating mode; and (2) send the proper lower 5-bit memory page addressto the Scrambler Address Input port. On memory accesses not starting atthe beginning of a memory page, the Starting Key Number Register shouldbe loaded with the proper Key value using a Control Register Accessoperation. After enabling the Control Register Access operating mode,the SKN Page Offset Register is loaded with the memory page address, theSKN Sector Offset Register is loaded with the memory column address, andoperation of the Scrambler is then switched to HW Flow Control.

The Scrambler may be controllable with parameter settings stored ascontrol data in the file system. Useful parameters include whether theScrambler is bypassed, whether the Scrambler default Seed is used oranother seed is loaded instead, and whether the shifter is enabled forcontinuous rotation or disabled, for example, for diagnostic purposes.Such configuration is preferably carried out on power-on initialization.

The figures of the previously-mentioned '905 application are alsoappropriate to describe certain memory systems and modules in accordancewith the present invention, by viewing the randomization module asdescribed therein as generally corresponding instead to a datascrambling module as described herein.

Referring now to FIG. 19, a table is shown listing memory cell states ofunscrambled repeating 0×FF data for the first 16 bytes of each word linewithin a memory block. FIG. 20 shows the scrambled memory cell states ofthe same first 16 bytes of each word line after scrambling as describedabove.

Additional Alternatives

In some embodiments, the system may perform a two-step memory readoperation, to first extract the SKN by reading with the descramblerdisabled and using the extracted SKN to look up the unscrambled key, andthen perform a second read with the descrambler enabled using theunscrambled SKN. However, this has implications to overall systemperformance and possible host timeout concerns. Other embodiments may bepossible which trade off system design issues and/or requirements. Forexample, the header or other control information need not necessarily bescrambled, while still preserving many of the advantages of randomizingthe data in a page. As another example, the SKN information may bestored unencrypted in the sector's header.

In some embodiments, the SKN could be stored, rather than the PageOffset value, in the page header. Alternatively, the entire initial Keyused for the page could be stored. These, as well as the Page Offsetvalue, could also be stored in a fully unscrambled manner, although thiswould create potentially undesirable data patterns down the bit lines.

The techniques for generating rotating scrambling keys described aboveare not the only manner of generating a deterministic sequence ofscrambling keys. Another method utilizes a linear shift feedbackregister (LFSR) to generate a pseudo-random sequence based upon aninitial seed. Such a seed can be associated with each page based uponeither the logical page address or physical page address in a similarmanner as described above. An exemplary use of a LFSR for randomizingdata in a flash memory is described in co-pending U.S. patentapplication Ser. No. 11/808,905, filed Jun. 13, 2007 by Sharon, et al,and entitled “Randomizing for Suppressing Errors in a Flash Memory,” thedisclosure of which is incorporated herein by reference in its entirety.

The descriptions above frequently make reference to registers forstoring certain values, such as the Page Offset Register for storing thePage Offset value. These refer to exemplary scrambler implementations,but are not to be viewed as limiting the more general discussion.

Memory pages frequently include 8-16 sectors, but other values may beused. Each sector typically includes 512 bytes of data and a sectorheader, and may also include ECC redundancy bytes. In some formats, asingle cluster of ECC bytes may protect more than one sector.

The block diagrams herein may be described using the terminology of asingle node connecting the blocks. Nonetheless, it should be appreciatedthat, when required by the context, such a “node” may actually representa pair of nodes for conveying a differential signal, or may representmultiple separate wires (e.g., a bus) for carrying several relatedsignals or for carrying a plurality of signals forming a digital word.As used herein, coupled means either directly or indirectly.

Terminology used herein that might be viewed as potentially limitingshould be viewed as merely descriptive of exemplary embodiments, and notlimiting of the invention itself. While the various embodiments havebeen described in the exemplary context of a non-volatile NAND memory,the invention is also useful for other types of memory devices,including volatile memory devices.

As used herein, the concept of a sequence of keys is really a functionof the implementation (e.g., only 32 bits at a time). For example, an8-key sequence of 8-bit keys, is really no different than a single64-bit key. For example, if a scrambler key is long enough, you mightneed only one for a chunk of data of a certain bit width, whereas forshorter keys, a sequence of keys may be required to fully scramble thechunk of data. In some embodiments, more than one seed key may be used,which might be determined, for example, based on the logical address.

The foregoing detailed description has described only a few of the manypossible implementations of the present invention. For this reason, thisdetailed description is intended by way of illustration, and not by wayof limitations. Variations and modifications of the embodimentsdisclosed herein may be made based on the description set forth herein,without departing from the scope and spirit of the invention. Moreover,the inventive concepts and embodiments described above are specificallycontemplated to be used alone as well as in various combinations. It isonly the following claims, including all equivalents, that are intendedto define the scope of this invention. Accordingly, other embodiments,variations, and improvements not described herein are not necessarilyexcluded from the scope of the invention.

What is claimed is:
 1. A method for storing information in anon-volatile memory, said method comprising: determining a starting keybased upon a seed key and a logical page address associated with a groupof data; randomizing the group of data using a deterministic sequence ofkeys corresponding to the starting key; storing the randomized group ofdata into a physical page of the non-volatile memory; and storing, intothe physical page of the non-volatile memory, additional informationfrom which the starting key may be determined without knowledge of thelogical page address, wherein the additional information is stored asrandomized information using the deterministic sequence of keyscorresponding to the starting key.
 2. The method as recited in claim 1further comprising: storing the additional information into more thanone location within the physical memory page, so that even if onelocation is corrupted, another can still be read to determine thestarting key.
 3. The method as recited in claim 1 wherein thedetermining comprises: determining an index for a sequence of scramblingkeys based upon a logical page offset value; and using the index toidentify the starting key within a repeating sequence of M-bitscrambling keys corresponding to the seed key.
 4. The method as recitedin claim 3 wherein: the additional information comprises the index.
 5. Amethod for storing information in a non-volatile memory said methodcomprising: determining a starting key based upon a seed key and alogical page address associated with a group of data; randomizing thegroup of data using a deterministic sequence of keys corresponding tothe starting key; storing the randomized group of data into a physicalpage of the non-volatile memory; and storing, into the physical page ofthe non-volatile memory, additional information from which the startingkey may be determined without knowledge of the logical page address,wherein the additional information comprises a mapped page offset codehaving a 1:1 correspondence with a page offset value.
 6. The method asrecited in claim 5 wherein: the mapped page offset code is identicalwith the logical page offset value, and may be directly read from thephysical page of the non-volatile memory without de-randomizing.
 7. Themethod as recited in claim 5 further comprising: determining a page codeassociated with the logical page offset value; and randomizing the pagecode using the deterministic sequence of keys corresponding to thestarting key, to generate the mapped page offset code which is stored inthe physical page of the non-volatile memory.
 8. The method as recitedin claim 7 wherein: the page code is randomized using only the startingkey, and the resulting mapped page offset code is written into a pageheader of the physical page of the non-volatile memory.
 9. The method asrecited in claim 7 wherein: the page code is determined by firmware; andthe page code is randomized by hardware.
 10. The method as recited inclaim 5 further comprising initializing the non-volatile memory uponpower-up, said initializing comprising: reading a randomized memory pageheader including a mapped page offset code; extracting a correspondingpage offset value from the mapped page offset code; then determining astarting key based upon the page offset value and the seed key; andreading and de-randomizing the memory page using a deterministicsequence of scrambling keys corresponding to the starting key.
 11. Themethod as recited in claim 10 wherein said extracting a correspondingpage offset value comprises using a lookup table.
 12. The method asrecited in claim 10 wherein said extracting a corresponding page offsetvalue comprises using a reverse mapping calculation.
 13. The method asrecited in claim 10 wherein said de-randomizing the memory pagecomprises de-randomizing at least the memory page header using firmware.14. The method as recited in claim 10 wherein said de-randomizing thememory page is performed using hardware.
 15. The method as recited inclaim 10 further comprising: re-constructing mapping of open blocks toidentify block types.
 16. The method as recited in claim 5 furthercomprising: determining a second starting key based upon the seed keyand a physical page address associated with a second group of data;randomizing the second group of data using a deterministic sequence ofkeys corresponding to the second starting key; and storing therandomized second group of data into a second physical page of thenon-volatile memory.
 17. The method as recited in claim 10 wherein saidinitializing is performed on blocks whose starting key is based upon itslogical page address and on blocks whose starting key is based upon itsphysical page address.
 18. The method as recited in claim 16 wherein:the second group of data corresponds to a control block of a flash filesystem.
 19. The method as recited in claim 5 further comprising:determining a third starting key based upon a predetermined default seedkey and a physical page address associated with a third group of data;randomizing the third group of data using a deterministic sequence ofkeys corresponding to the third starting key; and storing the randomizedthird group of data into a third physical page of the non-volatilememory.
 20. The method as recited in claim 1 further comprising: ECCencoding the randomized group of data and storing non-randomized ECCredundancy bytes in the non-volatile memory.
 21. The method as recitedin claim 1 further comprising: ECC encoding the non-randomized group ofdata to generate corresponding ECC bytes; randomizing the correspondingECC redundancy bytes; and storing randomized ECC redundancy bytes in thenonvolatile memory.
 22. The method as recited in claim 1 furthercomprising: randomizing all page header information written into thenon-volatile memory.
 23. The method as recited in claim 22 furthercomprising: randomizing control blocks for a flash file system using aphysical page address rather than a logical page address.
 24. The methodas recited in claim 22 further comprising: randomizing boot blocks for aflash file system using a predetermined default seed key, and using aphysical page address.
 25. The method as recited in claim 1 wherein thedeterministic sequence of keys comprises: a number M of separatescrambling keys, each comprising M-bits, wherein each respectivescrambling key N (KeyN) corresponds to an N-bit circular rotation of apredetermined seed key (Key0).
 26. The method as recited in claim 25wherein the randomizing comprises a bit-by-bit XOR operation using thedeterministic sequence of M-bit scrambling keys.
 27. The method asrecited in claim 26 wherein each successive scrambling key in thedeterministic sequence is a single-bit rotation of the precedingscrambling key.
 28. The method as recited in claim 26 wherein eachsuccessive scrambling key in the deterministic sequence is a bit-wiserotation of the seed key by a calculated number of bits.
 29. The methodas recited in claim 28 wherein the calculated number of bits for thesuccessive key depends on the current key.
 30. The method as recited inclaim 29 wherein the calculated number of bits for the successive keyalso depends on the page offset value and the D-word offset value of thecorresponding successive word.
 31. The method as recited in claim 1wherein the deterministic sequence of keys comprises: a pseudo-randomsequence of keys generated by a linear feedback shift register (LFSR)having a starting value corresponding to the starting key.
 32. Anapparatus comprising: a non-volatile memory; and a memory controllerconfigured to: determine a starting key based upon a seed key and alogical page address associated with a group of data; randomize thegroup of data using a deterministic sequence of keys corresponding tothe starting key; store the randomized group of data into a physicalpage of the non-volatile memory; and store, into the physical page ofthe non-volatile memory, additional information from which the startingkey may be determined without knowledge of the logical page address,wherein the additional information is stored as randomized informationusing the deterministic sequence of keys corresponding to the startingkey.
 33. The apparatus as recited in claim 32 wherein the non-volatilememory comprises a distinct integrated circuit separate from the memorycontroller.
 34. The apparatus as recited in claim 32 wherein the memorycontroller is further configured to: determine an index for a sequenceof scrambling keys based upon a logical page offset value; and use theindex to identify the starting key within a repeating sequence of M-bitscrambling keys corresponding to the seed key.
 35. The apparatus asrecited in claim 34 wherein: the additional information comprises theindex.
 36. An apparatus comprising: a non-volatile memory; and a memorycontroller configured to: determine a starting key based upon a seed keyand a logical page address associated with a group of data; randomizethe group of data using a deterministic sequence of keys correspondingto the starting key; store the randomized group of data into a physicalpage of the non-volatile memory; and store, into the physical page ofthe non-volatile memory, additional information from which the startingkey may be determined without knowledge of the logical page address,wherein the additional information comprises a mapped page offset codehaving a 1:1 correspondence with a page offset value.
 37. The apparatusas recited in claim 36 wherein the memory controller is furtherconfigured to: determine a page code associated with the logical pageoffset value; and randomize the page code using the deterministicsequence of keys corresponding to the starting key, to generate themapped page offset code which is stored in the physical page of thenon-volatile memory.
 38. The apparatus as recited in claim 37 wherein:the page code is randomized using only the starting key, and theresulting mapped page offset code is written into a page header of thephysical page of the non-volatile memory.
 39. The apparatus as recitedin claim 36 wherein the memory controller is further configured forinitializing the non-volatile memory upon power-up, said initializingcomprising: reading a randomized memory page header including a mappedpage offset code; extracting a corresponding page offset value from themapped page offset code; then determining a starting key based upon thepage offset value and the seed key; and reading and de-randomizing thememory page using a deterministic sequence of scrambling keyscorresponding to the starting key.
 40. The apparatus as recited in claim36 wherein the memory controller is further configured to: determine asecond starting key based upon the seed key and a physical page addressassociated with a second group of data; randomize the second group ofdata using a deterministic sequence of keys corresponding to the secondstarting key; and store the randomized second group of data into asecond physical page of the non-volatile memory.
 41. The apparatus asrecited in claim 39 wherein said initializing is performed on blockswhose starting key is based upon its logical page address and on blockswhose starting key is based upon its physical page address.
 42. Theapparatus as recited in claim 40 wherein: the second group of datacorresponds to a control block of a flash file system.
 43. The apparatusas recited in claim 36 wherein the memory controller is furtherconfigured to: determine a third starting key based upon a predetermineddefault seed key and a physical page address associated with a thirdgroup of data; randomize the third group of data using a deterministicsequence of keys corresponding to the third starting key; and store therandomized third group of data into a third physical page of thenon-volatile memory.
 44. The apparatus as recited in claim 32 wherein:the randomized group of data is ECC encoded and non-randomized ECCredundancy bytes are stored in the non-volatile memory.
 45. Theapparatus as recited in claim 32 wherein: all page header informationwritten into the non-volatile memory is randomized.
 46. The apparatus asrecited in claim 45 wherein: control blocks for a flash file system arerandomized using a physical page address rather than a logical pageaddress.
 47. The apparatus as recited in claim 45 wherein: boot blocksfor a flash file system are randomized using a predetermined defaultseed key, and using a physical page address corresponding to the bootblock.
 48. The apparatus as recited in claim 32 wherein thedeterministic sequence of keys comprises: a number M of separatescrambling keys, each comprising M-bits, wherein each respectivescrambling key N (KeyN) corresponds to an N-bit circular rotation of apredetermined seed key (Key0).
 49. The apparatus as recited in claim 48wherein the randomizing comprises a bit-by-bit XOR operation using thedeterministic sequence of M-bit scrambling keys.
 50. The apparatus asrecited in claim 49 wherein each successive scrambling key in thedeterministic sequence is a single-bit rotation of the precedingscrambling key.
 51. The apparatus as recited in claim 49 wherein eachsuccessive scrambling key in the deterministic sequence is a bit-wiserotation of the seed key by a calculated number of bits.
 52. Theapparatus as recited in claim 51 wherein the calculated number of bitsfor the successive key depends on the current key.
 53. The apparatus asrecited in claim 52 wherein the calculated number of bits for thesuccessive key also depends on the page offset value and the D-wordoffset value of the corresponding successive word.
 54. The apparatus asrecited in claim 32 wherein the deterministic sequence of keyscomprises: a pseudo-random sequence of keys generated by a linearfeedback shift register (LFSR) having a starting value corresponding tothe starting key.
 55. A method for storing information in a non-volatilememory, said method comprising: determining a starting key based upon aseed key and a logical page address associated with a group of data;randomizing the group of data using a deterministic sequence of keyscorresponding to the starting key; and storing the randomized group ofdata into a physical page of the non-volatile memory; wherein thedeterministic sequence of keys comprises a number M of separatescrambling keys, each comprising M-bits, wherein each respectivescrambling key N (KeyN) corresponds to an N-bit circular rotation of apredetermined seed key (Key0); wherein the randomizing comprises abit-by-bit XOR operation using the deterministic sequence of M-bitscrambling keys; wherein each successive scrambling key in thedeterministic sequence is a bit-wise rotation of the seed key by acalculated number of bits; and wherein the calculated number of bits forthe successive key depends on the current key and also depends on thepage offset value and the D-word offset value of the correspondingsuccessive word.
 56. An apparatus comprising: a non-volatile memory; anda memory controller configured to: determine a starting key based upon aseed key and a logical page address associated with a group of data;randomize the group of data using a deterministic sequence of keyscorresponding to the starting key; and store the randomized group ofdata into a physical page of the non-volatile memory; wherein thedeterministic sequence of keys comprises a number M of separatescrambling keys, each comprising M-bits, wherein each respectivescrambling key N (KeyN) corresponds to an N-bit circular rotation of apredetermined seed key (Key0); wherein the randomizing comprises abit-by-bit XOR operation using the deterministic sequence of M-bitscrambling keys; wherein each successive scrambling key in thedeterministic sequence is a bit-wise rotation of the seed key by acalculated number of bits; and wherein the calculated number of bits forthe successive key depends on the current key and also depends on thepage offset value and the D-word offset value of the correspondingsuccessive word.
 57. A method for storing information in a non-volatilememory, said method comprising: determining a starting key based upon aseed key and a logical page address associated with a group of data;randomizing the group of data using a deterministic sequence of keyscorresponding to the starting key; storing the randomized group of datainto a physical page of the non-volatile memory; and storing, into morethan one location within the physical page of the non-volatile memory,additional information from which the starting key may be determinedwithout knowledge of the logical page address.
 58. The method as recitedin claim 1, wherein the non-volatile memory comprises athree-dimensional memory.
 59. The method as recited in claim 58, whereinthe three-dimensional memory comprises more than one plane of memorycells stacked on top of each other.
 60. The method as recited in claim5, wherein the non-volatile memory comprises a three-dimensional memory.61. The method as recited in claim 60, wherein the three-dimensionalmemory comprises more than one plane of memory cells stacked on top ofeach other.
 62. The apparatus as recited in claim 32, wherein thenon-volatile memory comprises a three-dimensional memory.
 63. Theapparatus as recited in claim 62, wherein the three-dimensional memorycomprises more than one plane of memory cells stacked on top of eachother.
 64. The apparatus as recited in claim 36, wherein thenon-volatile memory comprises a three-dimensional memory.
 65. Theapparatus as recited in claim 64, wherein the three-dimensional memorycomprises more than one plane of memory cells stacked on top of eachother.
 66. The method as recited in claim 55, wherein the non-volatilememory comprises a three-dimensional memory.
 67. The method as recitedin claim 66, wherein the three-dimensional memory comprises more thanone plane of memory cells stacked on top of each other.
 68. Theapparatus as recited in claim 56, wherein the non-volatile memorycomprises a three-dimensional memory.
 69. The apparatus as recited inclaim 68, wherein the three-dimensional memory comprises more than oneplane of memory cells stacked on top of each other.
 70. The method asrecited in claim 57, wherein the non-volatile memory comprises athree-dimensional memory.
 71. The method as recited in claim 70, whereinthe three-dimensional memory comprises more than one plane of memorycells stacked on top of each other.